High-k dual dielectric stack

ABSTRACT

The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a field of semiconductor integratedcircuit (IC) manufacturing, and more specifically, to a device havingand a method of forming a high-k dual dielectric stack.

2. Discussion of Related Art

An integrated circuit (IC) may include various active devices andpassive devices. In particular, the IC may be designed using acomplementary metal-oxide-semiconductor (CMOS) technology that includesan NMOS transistor and a PMOS transistor. Other devices, such asresistors, capacitors, and inductors, may also be included.

A scaling down of dimensions of the integrated circuit (IC) depends on acombination of technical and economic factors. For over 40 years,Moore's Law has accurately tracked a doubling in density of the IC every18 months.

The transistors may be fabricated in a substrate on a wafer. Thesubstrate may be formed from a semiconductor material, such as Silicon.The transistors have a gate dielectric film. The gate dielectric filmmay be formed from an oxidation of the Silicon or by deposition of adielectric on the Silicon. The oxidation may be performed thermally. Theresultant gate oxide, such as SiO₂, has a dielectric constant, k, with avalue of 3.9.

Scaling down each succeeding generation of the IC requires a reductionin channel length and gate dielectric film thickness. However, leakagecurrent will also become larger.

In particular, a need exists for a gate dielectric film that is formedfrom a material with a higher value of k than the SiO₂.

The advancement of Moore's law may require other materials to replaceSilicon. However, the formation of high-k dielectric directly on GroupIII-V semiconductors may result in pinning of a Fermi-level at asurface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a device with a high-k dual dielectric stack according toan embodiment of the present invention.

FIG. 2 shows a device with a high-k dual dielectric stack with acomposite first gate dielectric according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following description, numerous details, such as specificmaterials, dimensions, and processes, are set forth in order to providea thorough understanding of the present invention. However, one skilledin the art will realize that the invention may be practiced withoutthese particular details. In other instances, well-known semiconductorequipment and processes have not been described in particular detail soas to avoid obscuring the present invention.

The present invention describes a method of forming a high-k dualdielectric stack and a device having the high-k dual dielectric stack.

As shown in an embodiment of the present invention in FIG. 1, a firstlayer 110 may be formed over a surface of a Group III-V componentsemiconductor material 100. The first layer 110 may include a dielectricmaterial that may unpin a Fermi level at a surface of the Group III-Vcomponent semiconductor material 100.

The first layer 110 may have a very limited thickness 115. The firstlayer may be ultra thin. In an embodiment of the present invention, thefirst layer may have a unit cell or monolayer thickness.

Next, a second layer 120 is formed over the first layer 110 to form ahigh-k dual dielectric stack 130. The second layer 120 should bechemically and physically compatible with the first layer 110. Thesecond layer 120 should be robust so as to protect the first layer 110.The second layer 120 should have a high dielectric constant k so anappropriate thickness 125 may be selected to allow scaling of anequivalent oxide thickness (EOT) 135 for the high-k dual dielectricstack 130.

As shown in an embodiment of the present invention in FIG. 2, a firstlayer 210 may be formed over the surface of the Group III-V componentsemiconductor material 200. The first layer 210 may include a compositeof two or more different dielectric materials, each of which may unpinthe Fermi level at the surface of the Group III-V componentsemiconductor material 200.

In an embodiment of the present invention, the composite may be ahomogeneous material with uniform properties.

In an embodiment of the present invention, the composite may be aheterogeneous material with discrete regions that differ incharacteristics.

The first layer 210 may have a very limited thickness. The first layer210 may be ultra thin. In an embodiment of the present invention, thefirst layer 210 may have a unit cell or monolayer thickness.

In an embodiment of the present invention, the formation of thecomposite of two or more different dielectric materials for the firstlayer 210 may be performed by co-deposition, such as by e-beamevaporation.

Next, a second layer 220 is formed over the first layer 210 to form ahigh-k dual dielectric stack 230. The second layer 220 should bechemically and physically compatible with the first layer 210. Thesecond layer 220 should be robust so as to protect the first layer 210.The second layer 220 should have a high dielectric constant k so anappropriate thickness 225 may be selected to allow scaling of anequivalent oxide thickness (EOT) 235 for the high-k dual dielectricstack 230.

In an embodiment of the present invention, the first layer 210 mayinclude Gadolinium Gallium Garnet (GGG) or Gd₂O₃(Ga₂O₃) while the secondlayer 220 may include Silicon Nitride or Si₃N₄. The second layer 220 maybe formed by jet vapor deposition (JVD). The jet vapor-deposited Si₃N₄film is compatible with the Gd₂O₃(Ga₂O₃).

An anneal temperature for the second layer 220 may depend on a stabilityof the first layer 210. The temperature limitation for the Si₃N₄directly deposited on the Group III-V component semiconductor material200 may only be 400-500 degrees Centigrade which is too low to achievethe best characteristics of the Si₃N₄.

However, an interface between the Gd₂O₃(Ga₂O₃) and the Group III-Vcomponent semiconductor material 200 may remain stable up to anannealing temperature of 780 degrees Centigrade. Consequently, thetemperature limitation for the Si₃N₄ deposited on the Gd₂O₃(Ga₂O₃) as abuffer layer for the Group III-V component semiconductor material 200may be as high as 750 degrees Centigrade.

The impact of bulk trap defects in the first layer 210 may be minimizedby selecting the ultra-thin or unit cell configuration of the firstlayer 210 since such a layer would contain a very few absolute number ofbulk trap defects. This allows a selection of a bulk-trap-defect-freesecond dielectric 220 without significant concern regarding an abilityof the second dielectric 220 to unpin the surface Fermi-level of theGroup III-V component semiconductor material.

The bulk trap defects in the first layer 210 may be removed byannealing, either before or after forming the second layer 220 over thefirst layer 210.

Should an imperfection exist in the first layer dielectric 210, aninfusion of the second layer dielectric 220 into the first layer 210 mayrepair the bulk trap defect or other imperfection in the underlyingfirst layer 210. The first layer 210 may have properties that wouldallow formation of a device that is compatible with CMOS technology.

In an embodiment of the present invention, a cluster tool may be usedfor formation of the high-k dual dielectric stack 230 of the presentinvention. After formation of the first layer 210 in a first chamber,the Group III-V component semiconductor material 200 may be transferredto a second chamber for depositing the second layer 220 in-situ so thatthe underlying first layer 210 would not be exposed to ambient, unlikein an ex-situ process, and thus would be protected from possibledegradation, such as by absorbing or reacting with air or water.

The selection of a thicker-than-monolayer second dielectric 220 willprovide a robust process for CMOS as it may protect the first dielectric210 from the moisture and chemical impacts of the process.

The present invention also envisions a high-k dual dielectric stack 230,such as for a depletion-mode or an enhancement-mode device. The high-kdual dielectric stack 230 includes a second layer 220 formed on a firstlayer 210. The first layer 210 may include Gadolinium Gallium Garnet(GGG) or Gd₂O₃(Ga₂O₃) while the second layer 220 may include Si₃N₄, suchas may be formed by jet vapor deposition (JVD).

The Fermi level at the surface of the Group III-V componentsemiconductor material 200 is normally pinned such that there is nosurface channel inversion. Such a surface channel inversion is neededfor operation of an enhancement-mode device thus limiting an ability touse the Group III-V component semiconductor 200 to replace Silicon toform a transistor for CMOS technology. Not many high-k dielectricmaterials can unpin a Fermi level at the surface of the Group III-Vcomponent semiconductor material 200.

One of the few possible candidate materials includes Gadolinium GalliumGarnet (GGG) or Gd₂O₃(Ga₂O₃). However, the properties of theGd₂O₃(Ga₂O₃) material may need to be optimized.

In an embodiment of the present invention, the ratio of Gadolinium toGallium in the first layer 210 may be altered to unpin the Fermi levelat the surface of the Group III-V component semiconductor material 200.

In an embodiment of the present invention, an internal crystallinestructure of the Gd₂O₃(Ga₂O₃) material may be optimized.

In an embodiment of the present invention, an external surfacemorphology of the Gd₂O₃(Ga₂O₃) material may be optimized.

Processing issues for the Gd₂O₃(Ga₂O₃) material may also have to beaddressed.

First, the Gd₂O₃(Ga₂O₃) material which is too thin may be unstable dueto absorption of moisture from the ambient or due to a sensitivity to achemical during processing.

Second, the Gd₂O₃(Ga₂O₃) material may only have a k value of 13-15, or arelative k-value to that of Silicon Oxide of 3.33-3.84, which may be toosmall to scale the EOT down to 3 nm or less.

Third, the Gd₂O₃(Ga₂O₃) material may include many bulk trap defects dueto deposition by e-beam evaporation on the surface of the Group III-Vcomponent semiconductor material 200.

The layer of Si₃N_(4.) may be free of pinholes even with a thickness ofonly 1-2 nm. Thus, the Si₃N_(4.) may protect the Gd₂O₃(Ga₂O₃) materialfrom moisture or a chemical during processing.

Scaling of the EOT 235 for the high-k dual dielectric stack 230 may beperformed by selecting a thickness 225 of the second layer 220 since itwill dominate the thickness 215 of the first layer 210.

In an embodiment of the present invention, the EOT 215 may be 3.30-3.75nm for the first layer 210. In an embodiment of the present invention,the EOT 225 may be 1.70-2.00 nm for the second layer 220. In anembodiment of the present invention, the EOT 235 may be 5.00-5.75 nm forthe high-k dual dielectric stack 230 of Gd₂O₃(Ga₂O₃)/Si₃N₄.

In an embodiment of the present invention, the EOT 215 may be 1.65-1.88nm for the first layer 210. In an embodiment of the present invention,the EOT 225 may be 0.85-1.00 nm for the second layer 220. In anembodiment of the present invention, the EOT 235 may be 2.50-2.88 nm forthe high-k dual dielectric stack 230 of Gd₂O₃(Ga₂O₃)/Si₃N₄.

In an embodiment of the present invention, the first layer 210 is amonolayer. In an embodiment of the present invention, the EOT 225 may beabout 1.00 nm for the second layer 220. In an embodiment of the presentinvention, the EOT 235 may be about 2.00 nm for the high-k dualdielectric stack 230 of Gd₂O₃(Ga₂O₃)/Si₃N₄.

Many embodiments and numerous details have been set forth above in orderto provide a thorough understanding of the present invention. Oneskilled in the art will appreciate that many of the features in oneembodiment are equally applicable to other embodiments. One skilled inthe art will also appreciate the ability to make various equivalentsubstitutions for those specific materials, processes, dimensions,concentrations, etc. described herein. It is to be understood that thedetailed description of the present invention should be taken asillustrative and not limiting, wherein the scope of the presentinvention should be determined by the claims that follow.

1. A method comprising: providing a Group III-V component semiconductormaterial; forming a first layer over a surface of said Group III-Vcomponent semiconductor material, said first layer to unpin a Fermilevel at said surface; forming a second layer over said first layer,said second layer for scaling an equivalent oxide thickness (EOT); andannealing said first layer before or after forming said second layer toremove bulk trap defects in said first layer.
 2. The method of claim 1wherein said first layer comprises a monolayer.
 3. The method of claim 1wherein said forming of said first layer comprises a co-deposition oftwo or more different dielectric materials.
 4. A device comprising: aGroup III-V component semiconductor material; and a high-k dualdielectric stack disposed over said Group III-V component semiconductormaterial, wherein said high-k dual dielectric stack comprises: a firstlayer, said first layer to unpin a Fermi level at a surface of saidGroup III-V component semiconductor material; and a second layerdisposed over said first layer, said second layer for scaling anequivalent oxide thickness (EOT).
 5. The device of claim 4 wherein saidfirst layer comprises: a monolayer.
 6. The device of claim 4 whereinsaid second layer comprises: a high-k dielectric with an EOT of 1.00 nm.7. The device of claim 4 wherein said high-k dual dielectric stackcomprises: an EOT of 2.00 nm.
 8. The device of claim 4 wherein saidfirst layer comprises: a monolayer that may be formed by co-depositionof two or more different dielectric materials, each of which may unpinthe Fermi level at the surface of the III-V component semiconductor. 9.The device of claim 4 wherein said first layer is a composite.
 10. Thedevice of claim 4 wherein said second layer dielectric may repair animperfection of said first layer dielectric.
 11. The device of claim 10wherein said imperfection of said first layer dielectric comprises abulk trap defect.